module MYAccumulator(
  input         clock,
  input         reset,
  input  [3:0]  io_accumIn_waddr,
  input         io_accumIn_wen,
  input         io_accumIn_wclear,
  input         io_accumIn_lastvec,
  input  [3:0]  io_raddr,
  input  [31:0] io_dataIn,
  output [3:0]  io_accumOut_waddr,
  output        io_accumOut_wen,
  output        io_accumOut_wclear,
  output        io_accumOut_lastvec,
  output [31:0] io_dataOut
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
`endif // RANDOMIZE_REG_INIT
  reg [31:0] mem [0:15]; // @[Accumulator.scala 38:30]
  wire  mem_MPORT_1_en; // @[Accumulator.scala 38:30]
  wire [3:0] mem_MPORT_1_addr; // @[Accumulator.scala 38:30]
  wire [31:0] mem_MPORT_1_data; // @[Accumulator.scala 38:30]
  wire  mem_io_dataOut_MPORT_en; // @[Accumulator.scala 38:30]
  wire [3:0] mem_io_dataOut_MPORT_addr; // @[Accumulator.scala 38:30]
  wire [31:0] mem_io_dataOut_MPORT_data; // @[Accumulator.scala 38:30]
  wire [31:0] mem_MPORT_data; // @[Accumulator.scala 38:30]
  wire [3:0] mem_MPORT_addr; // @[Accumulator.scala 38:30]
  wire  mem_MPORT_mask; // @[Accumulator.scala 38:30]
  wire  mem_MPORT_en; // @[Accumulator.scala 38:30]
  wire [31:0] mem_MPORT_2_data; // @[Accumulator.scala 38:30]
  wire [3:0] mem_MPORT_2_addr; // @[Accumulator.scala 38:30]
  wire  mem_MPORT_2_mask; // @[Accumulator.scala 38:30]
  wire  mem_MPORT_2_en; // @[Accumulator.scala 38:30]
  reg  mem_MPORT_1_en_pipe_0;
  reg [3:0] mem_MPORT_1_addr_pipe_0;
  reg  mem_io_dataOut_MPORT_en_pipe_0;
  reg [3:0] mem_io_dataOut_MPORT_addr_pipe_0;
  wire  _GEN_9 = io_accumIn_wclear ? 1'h0 : 1'h1; // @[Accumulator.scala 38:30 41:40]
  reg [3:0] io_accumOut_waddr_REG; // @[Accumulator.scala 50:37]
  reg  io_accumOut_wen_REG; // @[Accumulator.scala 51:37]
  reg  io_accumOut_wclear_REG; // @[Accumulator.scala 52:37]
  reg  io_accumOut_lastvec_REG; // @[Accumulator.scala 53:38]
  assign mem_MPORT_1_en = mem_MPORT_1_en_pipe_0;
  assign mem_MPORT_1_addr = mem_MPORT_1_addr_pipe_0;
  assign mem_MPORT_1_data = mem[mem_MPORT_1_addr]; // @[Accumulator.scala 38:30]
  assign mem_io_dataOut_MPORT_en = mem_io_dataOut_MPORT_en_pipe_0;
  assign mem_io_dataOut_MPORT_addr = mem_io_dataOut_MPORT_addr_pipe_0;
  assign mem_io_dataOut_MPORT_data = mem[mem_io_dataOut_MPORT_addr]; // @[Accumulator.scala 38:30]
  assign mem_MPORT_data = io_dataIn;
  assign mem_MPORT_addr = io_accumIn_waddr;
  assign mem_MPORT_mask = 1'h1;
  assign mem_MPORT_en = io_accumIn_wen & io_accumIn_wclear;
  assign mem_MPORT_2_data = $signed(io_dataIn) + $signed(mem_MPORT_1_data);
  assign mem_MPORT_2_addr = io_accumIn_waddr;
  assign mem_MPORT_2_mask = 1'h1;
  assign mem_MPORT_2_en = io_accumIn_wen & _GEN_9;
  assign io_accumOut_waddr = io_accumOut_waddr_REG; // @[Accumulator.scala 50:27]
  assign io_accumOut_wen = io_accumOut_wen_REG; // @[Accumulator.scala 51:27]
  assign io_accumOut_wclear = io_accumOut_wclear_REG; // @[Accumulator.scala 52:27]
  assign io_accumOut_lastvec = io_accumOut_lastvec_REG; // @[Accumulator.scala 53:28]
  assign io_dataOut = mem_io_dataOut_MPORT_data; // @[Accumulator.scala 48:20]
  always @(posedge clock) begin
    if (mem_MPORT_en & mem_MPORT_mask) begin
      mem[mem_MPORT_addr] <= mem_MPORT_data; // @[Accumulator.scala 38:30]
    end
    if (mem_MPORT_2_en & mem_MPORT_2_mask) begin
      mem[mem_MPORT_2_addr] <= mem_MPORT_2_data; // @[Accumulator.scala 38:30]
    end
    mem_MPORT_1_en_pipe_0 <= io_accumIn_wen & _GEN_9;
    if (io_accumIn_wen & _GEN_9) begin
      mem_MPORT_1_addr_pipe_0 <= io_accumIn_waddr;
    end
    mem_io_dataOut_MPORT_en_pipe_0 <= 1'h1;
    if (1'h1) begin
      mem_io_dataOut_MPORT_addr_pipe_0 <= io_raddr;
    end
    if (reset) begin // @[Accumulator.scala 50:37]
      io_accumOut_waddr_REG <= 4'h0; // @[Accumulator.scala 50:37]
    end else begin
      io_accumOut_waddr_REG <= io_accumIn_waddr; // @[Accumulator.scala 50:37]
    end
    if (reset) begin // @[Accumulator.scala 51:37]
      io_accumOut_wen_REG <= 1'h0; // @[Accumulator.scala 51:37]
    end else begin
      io_accumOut_wen_REG <= io_accumIn_wen; // @[Accumulator.scala 51:37]
    end
    if (reset) begin // @[Accumulator.scala 52:37]
      io_accumOut_wclear_REG <= 1'h0; // @[Accumulator.scala 52:37]
    end else begin
      io_accumOut_wclear_REG <= io_accumIn_wclear; // @[Accumulator.scala 52:37]
    end
    if (reset) begin // @[Accumulator.scala 53:38]
      io_accumOut_lastvec_REG <= 1'h0; // @[Accumulator.scala 53:38]
    end else begin
      io_accumOut_lastvec_REG <= io_accumIn_lastvec; // @[Accumulator.scala 53:38]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 16; initvar = initvar+1)
    mem[initvar] = _RAND_0[31:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  mem_MPORT_1_en_pipe_0 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  mem_MPORT_1_addr_pipe_0 = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  mem_io_dataOut_MPORT_en_pipe_0 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  mem_io_dataOut_MPORT_addr_pipe_0 = _RAND_4[3:0];
  _RAND_5 = {1{`RANDOM}};
  io_accumOut_waddr_REG = _RAND_5[3:0];
  _RAND_6 = {1{`RANDOM}};
  io_accumOut_wen_REG = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  io_accumOut_wclear_REG = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  io_accumOut_lastvec_REG = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module MYAccumulators(
  input         clock,
  input         reset,
  input  [3:0]  io_accumsIn_waddr,
  input         io_accumsIn_wen,
  input         io_accumsIn_wclear,
  input         io_accumsIn_lastvec,
  input  [31:0] io_datasIn_0,
  input  [31:0] io_datasIn_1,
  input  [31:0] io_datasIn_2,
  input  [3:0]  io_raddr,
  output [31:0] io_datasOut_0,
  output [31:0] io_datasOut_1,
  output [31:0] io_datasOut_2,
  output        io_done
);
  wire  MYAccumulator_clock; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_reset; // @[Accumulator.scala 69:23]
  wire [3:0] MYAccumulator_io_accumIn_waddr; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_io_accumIn_wen; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_io_accumIn_wclear; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_io_accumIn_lastvec; // @[Accumulator.scala 69:23]
  wire [3:0] MYAccumulator_io_raddr; // @[Accumulator.scala 69:23]
  wire [31:0] MYAccumulator_io_dataIn; // @[Accumulator.scala 69:23]
  wire [3:0] MYAccumulator_io_accumOut_waddr; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_io_accumOut_wen; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_io_accumOut_wclear; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_io_accumOut_lastvec; // @[Accumulator.scala 69:23]
  wire [31:0] MYAccumulator_io_dataOut; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_1_clock; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_1_reset; // @[Accumulator.scala 69:23]
  wire [3:0] MYAccumulator_1_io_accumIn_waddr; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_1_io_accumIn_wen; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_1_io_accumIn_wclear; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_1_io_accumIn_lastvec; // @[Accumulator.scala 69:23]
  wire [3:0] MYAccumulator_1_io_raddr; // @[Accumulator.scala 69:23]
  wire [31:0] MYAccumulator_1_io_dataIn; // @[Accumulator.scala 69:23]
  wire [3:0] MYAccumulator_1_io_accumOut_waddr; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_1_io_accumOut_wen; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_1_io_accumOut_wclear; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_1_io_accumOut_lastvec; // @[Accumulator.scala 69:23]
  wire [31:0] MYAccumulator_1_io_dataOut; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_2_clock; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_2_reset; // @[Accumulator.scala 69:23]
  wire [3:0] MYAccumulator_2_io_accumIn_waddr; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_2_io_accumIn_wen; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_2_io_accumIn_wclear; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_2_io_accumIn_lastvec; // @[Accumulator.scala 69:23]
  wire [3:0] MYAccumulator_2_io_raddr; // @[Accumulator.scala 69:23]
  wire [31:0] MYAccumulator_2_io_dataIn; // @[Accumulator.scala 69:23]
  wire [3:0] MYAccumulator_2_io_accumOut_waddr; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_2_io_accumOut_wen; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_2_io_accumOut_wclear; // @[Accumulator.scala 69:23]
  wire  MYAccumulator_2_io_accumOut_lastvec; // @[Accumulator.scala 69:23]
  wire [31:0] MYAccumulator_2_io_dataOut; // @[Accumulator.scala 69:23]
  MYAccumulator MYAccumulator ( // @[Accumulator.scala 69:23]
    .clock(MYAccumulator_clock),
    .reset(MYAccumulator_reset),
    .io_accumIn_waddr(MYAccumulator_io_accumIn_waddr),
    .io_accumIn_wen(MYAccumulator_io_accumIn_wen),
    .io_accumIn_wclear(MYAccumulator_io_accumIn_wclear),
    .io_accumIn_lastvec(MYAccumulator_io_accumIn_lastvec),
    .io_raddr(MYAccumulator_io_raddr),
    .io_dataIn(MYAccumulator_io_dataIn),
    .io_accumOut_waddr(MYAccumulator_io_accumOut_waddr),
    .io_accumOut_wen(MYAccumulator_io_accumOut_wen),
    .io_accumOut_wclear(MYAccumulator_io_accumOut_wclear),
    .io_accumOut_lastvec(MYAccumulator_io_accumOut_lastvec),
    .io_dataOut(MYAccumulator_io_dataOut)
  );
  MYAccumulator MYAccumulator_1 ( // @[Accumulator.scala 69:23]
    .clock(MYAccumulator_1_clock),
    .reset(MYAccumulator_1_reset),
    .io_accumIn_waddr(MYAccumulator_1_io_accumIn_waddr),
    .io_accumIn_wen(MYAccumulator_1_io_accumIn_wen),
    .io_accumIn_wclear(MYAccumulator_1_io_accumIn_wclear),
    .io_accumIn_lastvec(MYAccumulator_1_io_accumIn_lastvec),
    .io_raddr(MYAccumulator_1_io_raddr),
    .io_dataIn(MYAccumulator_1_io_dataIn),
    .io_accumOut_waddr(MYAccumulator_1_io_accumOut_waddr),
    .io_accumOut_wen(MYAccumulator_1_io_accumOut_wen),
    .io_accumOut_wclear(MYAccumulator_1_io_accumOut_wclear),
    .io_accumOut_lastvec(MYAccumulator_1_io_accumOut_lastvec),
    .io_dataOut(MYAccumulator_1_io_dataOut)
  );
  MYAccumulator MYAccumulator_2 ( // @[Accumulator.scala 69:23]
    .clock(MYAccumulator_2_clock),
    .reset(MYAccumulator_2_reset),
    .io_accumIn_waddr(MYAccumulator_2_io_accumIn_waddr),
    .io_accumIn_wen(MYAccumulator_2_io_accumIn_wen),
    .io_accumIn_wclear(MYAccumulator_2_io_accumIn_wclear),
    .io_accumIn_lastvec(MYAccumulator_2_io_accumIn_lastvec),
    .io_raddr(MYAccumulator_2_io_raddr),
    .io_dataIn(MYAccumulator_2_io_dataIn),
    .io_accumOut_waddr(MYAccumulator_2_io_accumOut_waddr),
    .io_accumOut_wen(MYAccumulator_2_io_accumOut_wen),
    .io_accumOut_wclear(MYAccumulator_2_io_accumOut_wclear),
    .io_accumOut_lastvec(MYAccumulator_2_io_accumOut_lastvec),
    .io_dataOut(MYAccumulator_2_io_dataOut)
  );
  assign io_datasOut_0 = MYAccumulator_io_dataOut; // @[Accumulator.scala 87:32]
  assign io_datasOut_1 = MYAccumulator_1_io_dataOut; // @[Accumulator.scala 87:32]
  assign io_datasOut_2 = MYAccumulator_2_io_dataOut; // @[Accumulator.scala 87:32]
  assign io_done = MYAccumulator_2_io_accumOut_lastvec; // @[Accumulator.scala 90:17]
  assign MYAccumulator_clock = clock;
  assign MYAccumulator_reset = reset;
  assign MYAccumulator_io_accumIn_waddr = io_accumsIn_waddr; // @[Accumulator.scala 76:46]
  assign MYAccumulator_io_accumIn_wen = io_accumsIn_wen; // @[Accumulator.scala 76:46]
  assign MYAccumulator_io_accumIn_wclear = io_accumsIn_wclear; // @[Accumulator.scala 76:46]
  assign MYAccumulator_io_accumIn_lastvec = io_accumsIn_lastvec; // @[Accumulator.scala 76:46]
  assign MYAccumulator_io_raddr = io_raddr; // @[Accumulator.scala 77:46]
  assign MYAccumulator_io_dataIn = io_datasIn_0; // @[Accumulator.scala 78:46]
  assign MYAccumulator_1_clock = clock;
  assign MYAccumulator_1_reset = reset;
  assign MYAccumulator_1_io_accumIn_waddr = MYAccumulator_io_accumOut_waddr; // @[Accumulator.scala 80:46]
  assign MYAccumulator_1_io_accumIn_wen = MYAccumulator_io_accumOut_wen; // @[Accumulator.scala 80:46]
  assign MYAccumulator_1_io_accumIn_wclear = MYAccumulator_io_accumOut_wclear; // @[Accumulator.scala 80:46]
  assign MYAccumulator_1_io_accumIn_lastvec = MYAccumulator_io_accumOut_lastvec; // @[Accumulator.scala 80:46]
  assign MYAccumulator_1_io_raddr = io_raddr; // @[Accumulator.scala 81:44]
  assign MYAccumulator_1_io_dataIn = io_datasIn_1; // @[Accumulator.scala 82:47]
  assign MYAccumulator_2_clock = clock;
  assign MYAccumulator_2_reset = reset;
  assign MYAccumulator_2_io_accumIn_waddr = MYAccumulator_1_io_accumOut_waddr; // @[Accumulator.scala 80:46]
  assign MYAccumulator_2_io_accumIn_wen = MYAccumulator_1_io_accumOut_wen; // @[Accumulator.scala 80:46]
  assign MYAccumulator_2_io_accumIn_wclear = MYAccumulator_1_io_accumOut_wclear; // @[Accumulator.scala 80:46]
  assign MYAccumulator_2_io_accumIn_lastvec = MYAccumulator_1_io_accumOut_lastvec; // @[Accumulator.scala 80:46]
  assign MYAccumulator_2_io_raddr = io_raddr; // @[Accumulator.scala 81:44]
  assign MYAccumulator_2_io_dataIn = io_datasIn_2; // @[Accumulator.scala 82:47]
endmodule
